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Electronic Design Process Symposium (EDPS) 2012
Thursday, April 5, 2012 at 8:30 AM - Friday, April 6, 2012 at 2:00 PM (PDT)
visit http://www.eda.org/edps for more information
of Silicon Valley
Electronic Design Process Symposium
April 5 & 6, 2012
Monterey Beach Hotel, Monterey, CA
The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves. Visit www.eda.org/edps.
Corporate Sponsors: Cadence • Synopsys • Mentor • Altera
- Mike Hutton, Principle Investigator, Office of the CTO, Altera
- Jim Hogan, Managing Partner, Vista Ventures
- Riko Radojcic, Dir. of Engineering, Qualcomm
(by Altera, Intel, AMD, ARM, Qualcomm, Broadcom, TSMC, Synopsys, Mentor, Cadence...)
- Top 5 EDA Problems
- EDA in the Cloud
- Low-Power with Performance
- 3D-IC Design Flow (Session)
- 3D-IC Design Flow (Panel)
On site Registration available April 5 & 6 - bring a check (no credit cards).
- Registration includes a copy of the workshop notes, continental breakfast on both days, lunch both days, and the EDP banquet dinner.
- You may bring a guest to the Banquet Dinner for $50.00. If you do, please pay when you first check into the meeting.
Important Web Sites:
Program Detail: (Printable 1-page PDF)
Announcement: (PDF emailer or for print)